1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing semiconductor device. Particularly, the present invention relates to a vertical MOSFET having a trench gate electrode and a method for manufacturing the same.
2. Description of Related Art
With rapid development of microfabrication technology, a semiconductor device continues to be integrated highly. Especially, it is well known that a vertical MOSFET (UMOSFET) having a gate electrode buried in a trench has low on-resistance and high breakdown voltage. Further, high integration is required for lower on-resistance and cost reduction (Japanese Unexamined Patent Application Publication No. 2005-86140 and No. 2001-36074). As one of methods for high integration, it is known that the gate trench is formed deeply in an epitaxial layer so as to shorten an aperture of the gate trench. For another method, it is known that an interlayer insulator is buried completely in the gate trench to shorten the aperture of the trench (Japanese Unexamined Patent Application Publication No. 2003-101027, No. 2000-252468 and U.S. Pat. No. 6,351,009).
Hereinafter, a related manufacturing process of UMOSFET, having the interlayer insulator buried in the gate trench completely, will be described. An N-channel type of UMOSFET is taken for instance. As shown in FIG. 9, an n− type epitaxial layer 82 is formed on a semiconductor substrate 81 by an epitaxial growth. A gate trench 83 is formed to the surface of the n− type epitaxial layer 82 so that the gate trench 83 reaches to the inner of the n− epitaxial layer 82. A gate insulator 84 is formed on the inner side of the gate trench 83. Further, a polysilicon 85 as a gate electrode is buried in the gate trench 83 with the gate insulator interposed therebetween. A high temperature oxide film (an HTO film) 86 is formed on the polysilicon 85 and the surface 82a of the n− type epitaxial layer.
A p type diffused base layer 87 and an n+ type diffused source layer 88 are formed on the surface 82a of the n− type epitaxial layer with ion implantation doping though the HTO film 86. A boron phosphorus silicate glass film (a BPSG film) 89 is formed on the HTO film 86. The BPSG film 89 has a flowability. Hence, the surface of the BPSG film 89 is planarized by a heat treatment after forming the BPSG film 89. An etch-back process is performed from the surface of the planarized BPSG film 89 to the depth of an aperture of the gate trench. So, the HTO film 86 and the BPSG film 89 formed on the n− type epitaxial layer 82 are removed. As shown in FIG. 10, a source electrode is formed on the entire surface of the semiconductor device. A drain electrode 91 is formed on the back side of semiconductor substrate 81. Hence, the cell pitch can be reduced, because the interlayer insulator (the BPSG film 89) between the gate electrode (the polysilicon 85) and the source electrode 90 is buried wholly in the gate trench 83.
In the UMOSFET configured as described above, the polysilicon 85 as the gate electrode is positioned in the lower portion of the gate trench 83. It is because the BPSG film 89 as the interlayer insulator is buried in the gate trench completely. Hence, it needs to form the n+ type diffused source layer 88 in the lower portion of the gate trench 83 depending on the position of the polysilicon 85. The process of heat treatment to planarize the BPSG film 89 includes the process to diffuse the n+ type diffused source layer 88 also in order to reduce number of process. Here, this process needs high temperature as to diffuse the n+ diffused source layer 88 sufficiently. However, the thickness of the HTO film 86 between the BPSG film 89 and the n− type epitaxial layer 82 is formed to be thin. It is because the p type diffused base layer 87 and the n+ type diffused source layer 88 are formed by ion implantation doping though the HTO film 86 as described above. Hence, if the heat treatment to planarize the BPSG film 89 is set to be high temperature, the diffusion of boron and phosphorus from the BPSG film 89 to the n− type epitaxial layer 82 is promoted. So, it makes the controllability of the manufacturing the semiconductor device worse.
In this way, the UMOSFET having the interlayer insulator buries in the gate trench has the process lower controllability, because impurity like boron and phosphorus diffuse from the BPSG film at the heat treatment.